EEL 5344 DIGITAL CMOS VLSI DESIGN

FALL  2008,  BSN 2205, MW: 3:05pm -4:20 pm

 

Instructor   Sanjukta Bhanja

Office: ENB 376/349 A, Office hours: MW 12:00 noon -1:00 pm  E-mail: bhanja@eng.usf.edu

 

  1. Prerequisites: Logic Design, Computer Organization and knowledge of Unix Environment.
  2. Course Textbook: `Principles of CMOS VLSI Design: A Systems Perspective,' N. Weste & K. Eshragian, Second Edition, Addison-Wesley, 1993, ISBN 0-201-53376-6.
  3. Announcements (Check blackboard)
  4. Syllabus
  5. Important Dates (Check blackboard)
  6. Important Academic policies
  7. Sample exams
  8. Educational experiments
  9. Tentative Outline

 

Dates

Topics

Notes

August 25, 27

Preliminary recaps, basic CMOS gates

Chapter 1

September 3, 8

CMOS memories, design abstraction, Virtuoso demo 1

Chapter 1

September  10, 15

Basic DC equation, Secondary effects, Demo 2

Assignment 1 posted, Chapter 2

September 17,  22

Inverters,  (CNT models)

Chapter 2

September  24, 29

 Circuit Characterization, Datapath Operations (adders,  decoders)

Chapter 4, 8

  October 1,  6

Resistance, capacitance, CMOS Processing (brief )

Chapter 4

   October 8, 13

Test 1, Inductance estimation, Datapath Operations (adders,  decoders)

Chapter 4, Chapter 8

October 15, 20

Switching Characteristics, Delay models

Chapter 4,  Project/Term paper posted

October 22,  27

Power dissipation, yield, reliability, Design margins

Chapter 4

October 29,  Nov.3

Spring break

Chapter 5, Chapter 8

November  5, 10

Test2, Physical design of logic gates, Datapath (multiplier), memory design

Chapter 5, Chapter 8

November 12, 17

CMOS logic families, FSMs, Clocking strategies

 Chapter 5,  6

November 19, 24

Simulations, VLSI Testing ,Testing, DFT

Chapter 7

November 26,  Dec. 1,

BIST, Scan-based testing, Test3, Nano-Ethics-Issues

Chapter 7

December 3,  8

Presentation, Presentation (extra)

In Class, Conference room

 

.

Assignments

  1. First assignment, Layout and simulation using Virtuoso and HSPICE simulator.

 

  1. Second assignment, Layout and simulation using Virtuoso and HSPICE simulator.

 

Tools

  1. CADENCE Virtuoso layout editor Handout  (Demo Date)
  2. CADENCE VERILOG Simulator Handout  (Demo Date)
  3. HSPICE simulator Handout  (Demo Date)