Introduction
CPU Interface
to an 8255 Bidirectional I/O Port
8255 Internal
Register Address Assignments
8255 Control Register
Memory Map
An 8255
Interfaced to a Single Board Computer
Chapter 11 Overview
Review Questions
Figure 11.1 8255 with DSP Circuit
Figure 11.2 8255 with 9016
in Control Register
Figure 11.3 Z80 CPU Interface to 8255
There are a several devices that are very useful when combined with a CPU. These are labeled as 8200 packages and are manufactured by Intel. There are three particular chips in this series that are immediately important, the 8250, the 8254 and the 8255. The 8250 is the Universal Asynhcronous Receiver and Transmitter (UART). This chip is the heart of the serial port card that in every computer. It provides a way for an 8 bit byte to be sent from a computer one bit at a time. The 8254 is a programmable counter package. It has three counters that can perform all of the functions of a 74161 plus many more. The 8255 is a programmable input/output port chip. It has three I/O ports that can be configured either as input or output ports. More details about the 8255 are provided below.
CPU Interface to an 8255 Bidirectional I/O Port
An excellent example of a peripheral interface that includes all of the concepts introduced to this point is the interface between a CPU and the 8255. This example is not only of educational but practical value. Today many computer interface boards are built around the versatile 8255.
Figure 11.1 brings the focus of the discussion to the 8255 and a way to generate its device select pulse. The figure shows a device that has three ports, Port A, Port B and Port C. The 8255 is a very popular device and is found on I/O boards that can be used in any IBM or IBM type computer. To enable the 8255 in this diagram address lines A6, and A7 must both be at logic 1 and pin 15, input G2, must be at logic 0.
The value of the 8255 is the fact that any or all of the ports can be used as input ports or as output ports. In fact, the direction of data through the port is determined by a pattern that resides in the 8255's control register. The exciting news is that the pattern in that control register can be changed.
Consider an IBM based, i.e an Intel built CPU, computer that has an 8255 I/O board. That computer will have 3 output ports if a specific pattern is placed in the 8255 control register. If that register's content is altered to a different specific pattern, then the 3 output ports will automatically be changed to 3 input ports. Consider the following binary pattern, 1001 00002. If this binary pattern for 90H is placed in the control register then the 8255 will configure Port A as an input port, Port B as an output port and Port C an output port. There are 256 possible patterns that could be placed into an 8255 control register. For now 90H will be the only pattern used in the discussion. Other possible port configuration patterns will be introduced later.
At this point, the pattern to be placed into the control register is not important. The big issue is the sequence of events that must be followed if the 8255 is to be configured in a desired manner. Suppose that your computer control application calls for Port A as an input port and Ports B and C as output ports. Take it for granted that the pattern that must be place in the control register to accomplish this task is the binary pattern for 90H. Again the real issue is how is the binary for 90H placed into the 8255's control register. It is constructive to use the circuit shown in Figure 11.1 as an example and then list the general mental groupings and the specific steps with in each group that must be taken to place that pattern for 90H into the 8255 control register.
(a) DATA BUS ACTIVITY
(2) Put a logic 0 on input G2.
8255 Internal Register Address Assignments
Table 18 provides
more details about the significance of the four possible 2 bit patterns
that could be placed on the 8255 input pins A1 and A0.
The table plus your general knowledge of how to read or write to a location
in a memory chip, should quickly help explain why the above ADDRESS BUS
ACTIVITY step (2) required that A0 and A1 both be
at logic 1. The information in Table 18 was provided by Intel. Trust
them, the check must be in the mail. They
assure the following to anyone who uses the 8255.
First; put the binary for 90H on the 8255 data pins, i.e. D7 through D0.
Second; bring the active low WR pin to 0 volts.
Third, put a logic 1 on A1 and A0.
Finally; bring the CS pin from logic 1 to logic 0.
Table 19 indicates the meaning of some of the 8 different bit places of the 8255 control register. Bit locations CR6, CR5 and CR2 will not be discussed at this time. The suggested logic states for these bits is logic 0. Something unexpected will happen to the 8255 if any of these bits are set, i.e. changed to logic 1. Table 19 is known as a bit map and is a convenient way to tell humans how to use a "smart" chip like the 8255. For example, control register bit CR4 indicates to the 8255 what direction Port A should be configured.
Figure 11.2 summarizes the example under discussion, the logic 1 value for bit CR4 means that Port A will be an input port. Control register bit CR1 indicates whether Port B should be an input port or an output port. The logic 0 value for CR1 means that Port B is an output port. The logic 0 values in CR0 and CR3 configure Port C as an output port. The logic 1 value for CR7 is required if the ports are to be configured in the manner stated.
It is actually possible to split Port C into two four bit ports. The 4 highest wires in the port, PC7, PC6, PC5 and PC4 are controlled by CR3. The least significant bit of the control register, CR0, indicates the direction of the lowest 4 bits, PC3, PC2, PC1, PC0, of Port C. For example if CR3 was at logic 1 and CR0 was at logic 0 then the lower nybble of Port C would a 4 bit output port, while the upper nybble of Port C would be a 4 bit input port.
The highest bit place in the control register, CR7, decides the mode of operation for the entire 8255. For now we will only consider the mode when CR7 is at logic 1, i.e. the BYTE MODE. Figure 11.2 shows the 8255 with the control register contents that configure it in its BYTE MODE with Port A as an input port with Port B and Port C as output ports.
An 8255 Interfaced to a Single Board Computer
Figure 11.3 shows the port configuration of a single board computer. The diagram does not show the CPU or the way the memory chips are connected to that CPU. The background information that has been provided thus far should make it easy to identify the 8255 and how it is interfaced to the missing CPU. Examine the diagram and determine what patterns would have to be placed on the CPU's Data bus, address bus and control bus to configure the 8255 so that port A is an output port with port B and port C as output ports.
Figure 11.3 is a schematic for a real interface from a Z80 CPU to a key board and display. The 8255 is a very popular chip for a variety of port interfacing tasks. This is actually a simple one. There are several interesting areas of the diagram.
On the left bottom section of Figure
11.3 one decoder of a dual decoder 74139 package is shown with its
2Y3 output connected to the CS terminal of the 8255. The input side
to the decoder has address lines A7
and A6 attached to B and A inputs,
respectively. There are also two labels to the left of A7 and
A6. The SH1 in front of both of these address lines indicate
where the two address signals are coming from. In this case, there
is another "sheet", i.e. diagram, that has the origin of the signals that
appear on A7 and A6 on the "sheet" in Figure 11.3.
( The "sheet" identification number is usually found in the label section
of a schematic.) Although you do not know what is on SH1, its a good gamble
that the CPU and its address, control and data bus connections are shown
in that schematic. Another observation to be made in the same area
of this diagram, is the absence of an IN or an OUT control bus wire connected
to the 74139. This among other things emphasizes the point that as
always, or at least as we always hope, the true wins out. For
now is a good time for me to offer a quick confession. Sometimes
I have fibbed to you. The truth is that the control bus for
the Z80 and many other CPU's does not actually have an IN or an OUT wire.
It usually has an IORQ or an IN/OUT Request wire. Believe me (as
opposed to my saying "trust me")this is not a major problem for your current
image of how device select pulse, DSP, circuits work. The CPU is able to
keep track of an INPUT vs an OUTPUT idea with its software commands.
There will be more on that issue later but for now, what physically happens
for this circuit when a DSP is generated is the following.
(b) The CPU generates a pulse on the IORQ control line.
(c) The CPU puts data, (the OUT idea) onto the data bus or the CPU takes data, ( the IN idea) from the data bus.
Although Figure 11.3 suggests that the CPU does not have an IN or an OUT control line it does imply the CPU does have a READ wire and a WRITE wire. These two control lines are shown in the left middle portion of the diagram as active low connections, RD and WR, to the 8255. In fact, they are also connected to 8255 pins labeled as RD and WR.
A fourth Z80 control line is also identified in that section of the diagram as RS1. This is a reset control line that the Z80 uses to synchronize its activates with various support chips. At this point the function of the RS1 control line and what the 8255 RS1 input pin does is of minimal concern. We may return to it later. There are several more control lines in the Z80 control bus. However since they are not used in this portion of the circuit they will not be discussed.
Most of the circuit to the right of the 8255 in Figure 11.3 has not been discussed yet. That portion of the circuit contains other simple input signal conditioning components that are easy to recognize but at this time may not be so easy to determine there use. The two invertors in package U3 at the bottom middle of the diagram are an example. It is clear that from an intellectual prospective there is not much sense in sending a signal into package U3 device "f" at pin 18, have it come out at pin 17 and then send it right back into device "e" at pin 11 only to come out at pin 10 to go into port A at PA7. That circuit action certainly has nothing to do with the logic of the signal. A signal that goes through two invertors has the same logic it started with. So what's the deal.
The answer to a double inversion circuit arrangements almost always has to do with signal conditioning not signal logic. The input label "EAR" to the right of the invertors is hard to read but it does represent an input signal coming from a tape recorder. Such signals are not good digital signals and do not even stay within the range of 0 volts to 5 volts. The double diode and resistor circuit elements between the invertor and the tape jack input do clean up the signal enough that the two invertors in series can provide a good TTL input signal to the PA7 input pin of the 8255. Note that the package is not the 7404 but the 74LS14. The LS is not the issue however, you should expect that the 7414 devices do the same logic operations but have significantly different electrical characteristics than the 7404's devices.
There are several other parts of the circuit in Figure 11.3 that will be of interest. The display in the upper right, the contact grid just above the 74LS14, the three other packages shown in the upper center, and the LED, resistor and speaker section to the center right of the schematic. We will return to these when the discussion of software issues is in full bloom.
11.1 Review Figure 11.1. Indicate what:
a) What binary pattern on the computer address bus will select
the chip select input of the 8255?
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 3 A2 A1 A0
b) What is the Hex value for that binary pattern?
c) What signal must be place on G2 to enable U9B?
d) What are the two steps a CPU must do to enable the 8255?
11.2 Examine the CPU to 8255 interface illustrated in Figure 11.3 very closely.
a) What CPU address lines are attached to the Read and Write pins of the 8255?
b) Does data flow from the CPU toward the 8255 or from the 8255 toward the CPU when the 8255 Write pin is active?
c) Does data flow from the CPU toward the 8255 or from the 8255 toward the CPU when the 8255 Read pin is active?
d) What voltage is required to activate the 8255 : 1) Read function? 2) Write function?
e) What CPU address lines are used to gain access to the 8255 Chip Select pin?
f) Examine Table 19 and determine in Hex. What is the:
1) the 8255 internal address for access to its control register?
2) the 8255 internal address for access to its port A data register?
3) the 8255 internal address for access to its port B data register?
4) the 8255 internal address for access to its port C data register?
g) What binary CPU address bus pattern will select the 8255 control
register 8255?
A15 A14 A13 12 A11 A10 A9 A8 A7 A6 5 A4 A3 A2 A1 A0
h) What is the Hex value for that binary pattern?