Figure 7.1 Memory Device (Simple Version)
Figure 7.2 7404 Connected to 7489 Output
Pins
There are a bundle of memory devices available to ordinary people like us. Each has a set of 3 or 4 letters as an identification label, WOM, ROM, RAM are just a few. Skipping forever the discussion about Write Only Memory, WOM, it is important to comment on the other two memory types. Read Only Memory, ROM, is the basic mainstay for computer applications that are to be used but not abused, i.e. not altered. Random Access Memory, RAM, and its close relatives, i.e. EPROM, DRAM, are of more interest. Our focus will just be on simple RAM memory and how it is accessed for either read or write.
Figure 7.1 shows an over simplified RAM memory device. It has pins assigned as Address, Control and as Data Bus connections. This specific example actually has an input data bus and an output data bus. It has four address lines and three control lines. The power and ground connection are not shown for this device.
The basic operation of a RAM memory really does follow the same sequence you or I would do to read something from or write something to a notebook. If you wish to enter a number into your notebook, you would have to access a page in the book,(select, enable, the memory chip), pick a location on the selected notebook page,(select a memory location in the selected memory chip) and finally write something on the paper at the selected location,(activate the WRITE pin).
An examination of the RAM memory device in Figure 7.1 indicates the width of the data bus, 4 bits, and the number of memory locations, 16, in the chip. The four specific steps to write the pattern 4H into this RAM at location D are as follows.
a) Put the four bit pattern 0100 onto data input pins DI3, DI2, DI1, and DI0, respectively.
b) Put the four bit pattern 1101 onto address pins A3, A2, A1 and A0, respectively.
c) Put 0 volts on the WRITE ENABLE pin, WE.
d) Put 0 volts on the MEMORY ENABLE pin, ME.
The order of the first three steps in this process could be up for discussion but whatever that order the last step is to enable the device.
Reading a memory chip is only a three step process. The specific steps to read a pattern from memory location A in the RAM shown in Figure 44 are as follows.
a) Put the four bit pattern 1010 onto address pins A3, A2, A1, and A0, respectively.
b) Put 0 volts on the READ ENABLE pin, RE.
c) Put 0 volts on the MEMORY ENABLE pin, ME.
The read process takes one less step than a write process simply because in the read operation the data is taken from the memory location and placed on the data bus. In this case, once step (c) is done, the memory chip will put a copy of the four bit pattern 1011 from memory location A, Figure 7.1, onto output data pins DO3, DO2, DO1, and DO0, respectively.
Figure 7.2 shows a circuit with the 7489 RAM memory chip. It is similar to the general device shown in Figure 7.1 with the exception of one less control wire. It is common to have the READ and the WRITE functions defined by just one pin. It guarantees that the memory chip, once enabled, will have to perform the READ or the WRITE function. A quick look at pin 3 will indicate another common practice.
The WRITE function on the 7489 is the one that is active low. This is just one more precaution to assure that the chip does not get enabled in the WRITE mode unless that is what the user wished. Remember that TTL devices will always try to bring input pins to logic 1. Thus if the wire connection to pin 3 was broken the pin would "drift" to logic 1. Since the WRITE function is active low the READ function is active high. This assures that the memory chip defaults to its READ mode unless pin 2 is actually at 0 volts.
There is one more little trick illustrated in Figure 7.2. The output data bus pins are attached to the inputs of a 7404. This is a cheap way to handle two characteristics of the 7489. The first is the fact that the four output pins present the inverse of the contents of the memory location being read. (This is one of the few time that the circles mean inversion. However, it is not the first time you have seen that. Remember that there is a circle on the inverting output pin on the 7474 Flip Flop diagram.) By placing an invertor on each of the memory chip output pins the pattern detected on the LED's will be the same pattern that was stored in the memory location.
The second characteristic of the 7489 and the second reason the 7404 is included in the circuit is a little more subtle. The 7489 has open collector outputs. Since output pins of more than one memory chip are always connected together, there has to be some way to guarantee that commonly connected output pins are not at opposite voltages at the same time. In other words two normal TTL output pins can not be connected together if there is any chance that one of those output pins might be at 5 volts when the other output pin is at 0 volts.
There are two ways to assure that such voltage combinations will not happen to multiple memory chips that have output pins that are physically tied together. Those memory chips must have either open collector or 3 state outputs. The 7489 was one of the first TTL memory devices made and the 3 state output was not available at that time. Therefore the 7489 has open collector output pins.
Basically open collector devices have output pins that can only produce a logic 0 signal and the logic "nothing" signal. The logic "nothing" signal is the signal that you would have on a piece of wire that was not electrically connected to anything. It would be just a piece of wire that has no electrical signal, i.e the logic nothing signal, associated with either of its ends. (Please read the note section entitled 3 State and Open Collector Devices if more details are required at this time.) Therefore, if the pattern in memory location A of the 7489 in Figure 7.2 was the same as the pattern shown in Figure 7.1, the actual signals that would show up on the 7489 output pins are shown in Table 17.
The interesting information in the table is not the 0V signals at DO3, DO1, and DO0 but the "no signal" on DO2. The invertor inputs shown in Figure 7.2 as pins 9, 3, and 1 will easily change the 0 volt signals at these pins to logic 1's at 7404 output pins 8, 4 and 2, respectively. The issue is really centered on what happens at pin 9 of the 7489.
The answer is actually simple. Since the logic state at pin 9 of the 7489 is the logic "nothing" state, the corresponding connected 7404 input pin, pin 5, does not sense any signal at all. From the 7404 prospective, that input pin does not have a voltage on it. Therefore, pin 5 on the 7404 "drifts" to logic one and the corresponding 7404 output goes to logic 0. Thus the actual logic pattern present on the 7404 output pins is the same pattern that is resident in memory location A.
7. 1 Review Figure 7.2. Draw a function diagram for an experimental circuit that will allow you to study the operation of the 7489. Use numbered switches on the address pins and input data pins. Use numbered LEDs for output data pin displays. Use the appropriately active high or low push button for connection to each of the control lines.