Figure 9.1 Function Diagram
for Device Select Pulse Circuit
Figure 9.2 Simplified Memory
Select Pulse Circuit
Introduction
At this point it is useful to introduce some of
the details concerning the interface between the CPU and the devices it
needs so it can function as a complete computer. The CPU, ( an 80486,
80386, 80286, 8088, Z80 or the 8080 for example), requires connection to
input ports, output ports and memory devices. The way this is done
really is quite clever. The CPU puts patterns on its address bus
and control bus so that specific devices can be selected. The selected
device is then prepared to receive data from the CPU via the data bus or
send data to the CPU via the same data bus. The discussion about
CPU interfacing will begin with the I/O interface and then follow with
one example of a CPU to memory interface.
Figure 9.1 provides a general overview of a computer I/O structure. A quick look at this diagram will suggest that all of its parts have been discussed. The trick now is to appreciate the role of the parts as they function to perform the whole idea. There are three old ideas in the figure ( i.e the device select pulse, the input port, and the output port) and there is one new concept, the computer bus.
The computer bus is a straight forward image. A bus is a collection of wires that are attached to the CPU, i.e. the microprocessor chip, that perform the same type of task. The data bus has the responsibility of transferring information to and from the internal CPU registers to and from the I/O ports. A Computer data bus is bidirectional. The address bus is a set of wires that sends address patterns from the CPU to decoders, memory chips, and other devices that support the CPU's role.
The third common bus is the control bus. This collection of wires send control signals from the CPU to support devices. Four common labels for control bus wires are IN, OUT, READ and WRITE. Other control wire labels include INTERRUPT ACKNOWLEDGE and I/O REQUEST. The names for control wires varies with the manufacturer of the CPU, i.e Motorola and Intel, and the type of CPU, i.e Z80, 8080, 80386, 80486,etc. Usually the name easily reflects the function that the CPU uses that wire to control.
The three buses are labeled and shown in at Figure 9.1. The control bus and the address bus are at the bottom but the CPU is not shown in the diagram. This is a common practice especially if the diagram is focused on the CPU's peripheral devices. The devices selection pulse portion of Figure 9.1 is also located in the bottom section of the diagram. Figure 4.3 provides an alternate illustration of a device select pulse circuit. In that figure, a 74138 is used together with 4 independent AND devices. The outputs to the AND's are connected to the active high starter circuits for four different motors, motor #0, motor #1, motor #2 and motor #6. If the intent was to run motor number zero, then the code for channel zero, 0,0, 0 is sent to inputs A,B,C. For that circuit, switches S0, S1, and S2 must all be held closed. Once this is accomplished, motor #0 will start if S4 is open. If S4 is held closed the motor will not start. The crude circuit in Figure 4.3 illustrates the two concepts needed to generate a device select pulse.
First, there is an address selection procedure.
Second, that process is followed by the generation of a pulse signal on a control line.
The three switches, S0, S1, and S2 , with their corresponding wires attached to the 74138 input pins are essentially a human controlled three wire address bus while the single wire attached from S4 to the input of all four separate AND gates acts as a one wire human operated control bus. The device select pulse is generated when the pattern put on the address bus is decoded and then combined with a pulse that has been sent down the control line. This combination of activity on the address bus and the control bus generates a device select pulse. This device select pulse is unique to a specific input or output port.
Generic Requirements for I/O to CPU Interface
The device select pulse circuit shown in Figure 9.1 is a generic representation to indicate how the computer's input and output ports are controlled by the CPU. This is accomplished in a three step process;
First, address patterns generated by the CPU are presented to the inputs of a decoder.
Second, the decoder interprets the pattern and selects one of its output channels to go active. In this case the channel goes low when selected.
Finally, at almost the same instant of time, the CPU also places a pulse on one of its control lines. This pulse together with the low signal from the selected decoder output pin transmit the pulse to the selected device.
In the specific case depicted in Figure 9.1, there are only three possible target devices for the device select pulse. If the CPU puts the binary pattern for 110 on the address bus then decoder output channel 1 goes low. This signal is sent and held at one of the low active input wires of the logic operation shown as the middle logic device in the diagram. The other input signal to that logic operation is a pulse on the IN control wire. Together these two signals provide a pulse labeled DSP 1 to the combination 3 state device/data follower device that isolates the flow meter data output circuitry from the CPU's data bus.
Another device select pulse circuit illustrated in Figure 9.1 combines the output signal from channel 0 of the decoder with an OUT pulse from the control bus to generate DSP 0. This pulse isolates the printer from the CPU's data bus. The third device select pulse, DSP 255, is generated when the CPU puts FFhex on the 8 bit address bus and sends a negative leading edge pulse to its IN control line.
For all three of the DSP circuits in Figure 9.1, the CPU co-ordinates the combination of address pattern and control line pulse so that the data is taken into or released from a CPU register at just the right instant of time. For example, OUT DSP 0 is generated for the exact period of time that is required for the CPU to transfer the data byte, usually an ASCII character, from its register to the data bus and then have the printer take that byte from the data bus and put it into its printer buffer.
In summary, this is the first pass at a very important concept. There are two distinctive actions that must be taken to allow data to come to or go from a CPU via an input or output port.
First an address pattern unique to the I/O port must be placed on the CPU's address wires.
Second, a pulse signal must be placed on one of the CPU's control wires.
It is also important to note that the diagram in Figure 9.1 is really only an educational function diagram. It emphasizes the important intellectual components needed if a computer CPU is to coordinate its internal activities with the external world. It does not represent an actual circuit that would be used as a CPU to I/O interface in today's computers . We will return to this issue later in the course.
Understanding how to read to or write from a memory device is essential background knowledge. However from a practical computer usage point of view, all of the electrical signals to the address bus and the control bus are taken care of in software. The data will flow the correct direction on the data bus if the software command is selected properly. A more long term need for Chemical and Mechanical engineers that wish to incorporate real world equipment into a computer control system is the understanding of how memory chips in a computer system are arranged and selected for READ/WRITE activities. This type of knowledge will allow for system alterations so that some memory locations can be reconfigured as input and output ports. The reasons for doing this reconfiguration will be discussed later.
Figure 9.2 illustrates
an abbreviated and simplified memory device select circuit for a set of
memory chips. Only one memory chip is shown in the diagram but the
general circuit idea could be used to enable up to 256 chips for read/write
activity. One constructive way to study this diagram is to compare it to
the I/O device select circuit in Figure 9.1.
The memory device select circuit is only slightly more complicated but
still has the same select strategy as the I/O device select circuit.
The most apparent difference is the addition of an OR concept in Figure
9.2. This allows either the READ or the WRITE function
to be initiated but still prevents more than one memory chip from being
selected and one location be accessed at time.
9. 1 Review Figure 9.1 What
a) pattern has to be placed on the address bus to send a data byte to the printer?
A15 A14
A13 A12
A11 A10
A9 A8
b) control line will require the application of a square wave if the
printer is to be accessed?
9. 2 Review Figure 9.2 What
a) pattern has to be placed on the address bus to prepare Memory Chip #0 to read or write?
A15 A14
A13 A12
A11 A10
A9 A8
b) control line will require the application of a square wave if Memory
Chip #0 is to perform a read operation.
c) pattern has to be placed on the address bus to prepare Memory Chip #0 to read to or write from location 33?
A7 A6 A5 A4 A3 A2 A1 A0