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Computer Logic Design Lab (CDA3201L)
FALL 2003
Lab Exercise 5

Latches and Flip Flops

Experiments 1, 2, 3 on bread board and LogicWorks.

1. Design and implement basic NAND implementation of gated S-R Latch. Verify the operation of the latch. Timing simulation should be done in LogicWorks.

2. Verify the operation of JK 7476 flip-flop. Connect the JK inputs to the DIP switches and clock input to function generator. Connect the output to resistor-LED and also to Oscilloscope. Draw timing diagram for all possible combinations of JK inputs as you see on oscilloscope. Timing simulation should also be done in LogicWorks.

3. Verify the operation of D (7474) flip-flop. Connect the D input to the DIP switch and clock input to function generator. Connect the output to resistor-LED. Perform timing simulation for all possible combinations of D input in LogicWorks. 

Experiments 4, 5 in LogicWorks only 

4. Design basic NOR implementation of gated S-R Latch. Verify the operation of the latch. Timing simulation should be done in LogicWorks.

5. Design a TFF using DFF with external gating. Perform timing simulation in LogicWorks.

Q & A

1. Draw ideal and practical timing diagram for NAND and NOR SR Latch.

2. Explain why SR latch won't work for combination of S=1 and R=1. How can we eliminate this unknown case.

IMPORTANT: Bring your Bread board implementation and LogicWorks circuit file to the lab. Lab grade will depend on the working of the circuit and will be checked off by the lab instructor.