Low Power CMOS VLSI Design (EEL 6936-002)

Tentative Outline

Dates	Topics	Notes
January 8, 10	Physics of Semiconductors	Chapter 2
January 17	Power Models, Dynamic, Short Circuit, Leakage, Design Limits in Nano domain	Chapter 2
January 22, 24	Power Estimation	Chapter 3
January 29 31	HSPICE Demo, Signal Probability	Chapter 3
February 5, 7	BDD, Transition density, simultaneous switching	Assignment 1 posted, Chapter 3
February 12, 14	Statistical simulation, maximum power	Test 1, Chapter 3
February 19, 21	Sequential circuits, Sample exams	Chapter 4,
February 26, 28	Power optimization (Behavioral, RT) power optimation(Logic),	Assignment 1 due, Assignment 2 posted, Chapter 4
March 5, 7	Transister level optimization, low power synthesis	Chapter 4
March 19, 21	Power Optimization, technology mapping	Term paper abstract due, Test 2, Chapter 4
March 26, 28	Leakage power, Low Vdd, multiple Vth designs	Assignment 2 due, Chapter 5
April 2, 4	Leakage power, Low Power Memory	Chapter 5
April 9, 11	Energy Recovery	Chapter 8
April 16, 18	Term Paper Presentation
April 23, 25	Term paper presentation	Test 3

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Assignments First assignment, Second assignment,

Tools CADENCE Virtuoso layout editor Handout CADENCE VERILOG Simulator Handout HSPICE simulator Handout HSPICE netlist format